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ADT7467
HIGH LIMIT
TEMPERATURE
Masking Interrupt Sources
Interrupt Mask Registers 1 and 2 are located at Address
0x74 and Address 0x75, respectively, and allow individual
interrupt sources to be masked to prevent SMBALERT
“STICKY”
STATUS BIT
SMBALERT
TEMP BACK
IN LIMIT
(STATUS BIT
STAYS SET)
CLEARED ON READ
(TEMP BELOW
LIMIT)
interrupts. Note that masking an interrupt source prevents
only the SMBALERT output from being asserted; the
appropriate status bit is set normally.
Table 21. INTERRUPT MASK REGISTER 1
(REG. 0X74)
Figure 27. SMBALERT and Status Bit Behavior
Figure 27 shows how the SMBALERT output and sticky
status bits behave. Once a limit is exceeded, the
corresponding status bit is set to 1. The status bit remains set
until the error condition subsides and the status register is
read. The status bits are referred to as sticky because they
remain set until read by software. This ensures that an
out-of-limit event cannot be missed if software is polling the
device periodically. Note that the SMBALERT output
remains low both for the duration that a reading is out of limit
and until the status register has been read. This has
implications on how software handles the interrupt.
Bit
7
6
5
4
2
0
Mnemonic
OOL
R2T
LT
R1T
V CC
V CCP
Description
1 masks SMBALERT for any alert
condition flagged in Status Register 2.
1 masks SMBALERT for Remote 2
temperature channel.
1 masks SMBALERT for local
temperature channel.
1 masks SMBALERT for Remote 1
temperature channel.
1 masks SMBALERT for the V CC
channel.
1 masks SMBALERT for the V CCP
channel.
Handling SMBALERT Interrupts
To prevent the system from being tied up with servicing
interrupts, it is recommend to handle the SMBALERT
Table 22. INTERRUPT MASK REGISTER 2
(REG. 0X75)
interrupt as follows:
1. Detect the SMBALERT assertion.
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt
source.
4. Mask the interrupt source by setting the
appropriate mask bit in the interrupt mask registers
(Register 0x74 and Register 0x75).
5. Take the appropriate action for a given interrupt
source.
6. Exit the interrupt handler.
7. Periodically poll the status registers. If the
interrupt status bit has cleared, reset the
Bit
7
6
5
4
3
2
1
Mnemonic
D2
D1
FAN4
FAN3
FAN2
FAN1
OVT
Description
1 masks SMBALERT for Diode 2 errors.
1 masks SMBALERT for Diode 1 errors.
1 masks SMBALERT for Fan 4 failure. If
the TACH4 pin is being used as the
THERM input, this bit masks
SMBALERT for a THERM event.
1 masks SMBALERT for Fan 3.
1 masks SMBALERT for Fan 2.
1 masks SMBALERT for Fan 1.
1 masks SMBALERT for
overtemperature (exceeding THERM
limits).
corresponding interrupt mask bit to 0. This causes
the SMBALERT output and status bits to behave
as shown in Figure 28.
HIGH LIMIT
TEMPERATURE
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt function is disabled by
default. Pin 5 or Pin 9 can be reconfigured as an
SMBALERT output to signal out-of-limit conditions.
Table 23.
CONFIGURING PIN 5 AS SMBALERT OUTPUT
Register
Bit Setting
“STICKY”
STATUS BIT
SMBALERT
CLEARED ON READ (TEMP BELOW
LIMIT)
TEMP BACK
IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
Configuration Register 3 (0x78) <0> ALERT Enable = 1
Assigning THERM Functionality to a Pin
Pin 9 on the ADT7467 has four possible functions:
SMBALERT, THERM, GPIO, and TACH4. The user
INTERRUPT MASK BIT CLEARED
(SMBALERT REARMED)
Figure 28. Effect of Masking the Interrupt Source on
chooses the required functionality by setting Bit 0 and Bit 1
of Configuration Register 4 at Address 0x7D.
SMBALERT Output
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